1. Field of the Invention
This disclosure relates to a nonvolatile semiconductor memory device having an electric erasable/programmable function, and more particularly, to a NAND Structure nonvolatile semiconductor memory device having electrically erasable and programmable memory cells.
2. Description of the Related Art
Generally, semiconductor memory devices are classified into two groups, that is, volatile semiconductor memory devices and a nonvolatile semiconductor memory devices. Volatile semiconductor memory devices can be further classified into a dynamic random access memory and a static random access memory. Volatile semiconductor memory devices have rapid speed in writing and reading, but have a disadvantage that contents stored in memory cells are erased when electric power supply is cut off.
Nonvolatile semiconductor memory devices are classified into mask read only memorys (MROM), programmable read only memorys (PROM), erasable and programmable read only memorys (EPROM), and electrically erasable programmable read only memorys (EEPROM). Since a nonvolatile semiconductor memory device permanently stores any contents in the memory cells even though an external electric power supply is cut off, the device is mainly used in storing contents that are required to remain therein irrespective of whether electric power is supplied or not.
However, a user cannot perform reading and writing (or programming) without restraint through an electronic system provided with the MROM, PROM, and EPROM. That is, it is not easy for a user to erase or reprogram contents programmed on-board. In contrast, since the EEPROM can perform electrically erasing and writing operations in its system itself, it has been applied and will continuously be applied as a system program storing device or a sub-memory device that need to have their contents continuously renewed.
In other words, various electronic systems being controlled by a recent computer or microprocessor have required an improved EEPROM having accurately erasable and programmable functions. Furthermore, since a battery powered computer system having a notebook size or portable computer size employs a hard disk device having a rotational magnetic disk occupying a relatively large area as a supplementary memory device, designers designing such systems have been very interested in developing a high integrated and high performance EEPROM, having a relatively small size.
It is very important to reduce the area occupied by memory cells in order to accomplish a high integrated EEPROM. In order to solve such a problem, an EEPROM having memory cells with a NAND structure, by which the number of select transistors per cell and the number of contact holes contacted with bit lines can be reduced, has been developed. As an example, such a NAND structure cell has been disclosed in pages 412 to 415 of IEDM under the title of xe2x80x9cNEW DEVICE TECHNOLOGIES FOR 5V-ONLY 4 Mb EEPROM WITH NAND STRUCTURE CELLxe2x80x9d, which is hereby incorporated herein.
Such a NAND structure cell will be explained below to provide better understanding for the present invention to be explained later.
The above-mentioned NAND structure cell consists of a first select transistor, a second select transistor, a source of which is coupled to a common source line, and eight memory transistors channels of which are in series connected between the source of the first select transistor and the drain of the second select transistor. The NAND structure cells are formed on a P type semiconductor substrate, and each of the memory transistors has a floating gate formed by forming a gate oxide film on a channel region between the source region and drain region and a control gate formed on the floating gate through an interlayer insulating layer. In order to program a memory transistor selected within the NAND cell unit, all of the memory transistors within the cell unit are erased, then programming operations are performed. The erasing operations of all of the memory transistors (generally called a flash erasing operation) are performed at the same time by applying 0 Volts to bit lines and, approximately 17 Volts to a gate of the first select transistor and control gates of all of the memory transistors. That is, all the memory transistors are converted to enhancement mode transistors, which are assumed to be transistors programmed by a binary digit xe2x80x9c1xe2x80x9d.
In order to program the selected memory transistors with a binary digit xe2x80x9c1xe2x80x9d, approximately 22 Volts is applied to bit lines, a gate of the first select transistor, and a control gate of each of the memory transistors between the first select transistor and the selected memory transistors. And, 0 volts is applied to a control gate of the selected memory transistor, a gate of the second select transistor and a control gate of each of the memory transistors between source lines and the selected memory transistors. Therefore, the selected memory transistor is programmed from a drain thereof to a floating gate by Fowler-Nordheim F-N tunneling of holes.
However, such a programming method has a problem in that a gate oxide film is stressed by a high voltage applied to a drain of the selected memory transistor and the stressed gate oxide layer accordingly causes current leakage there through. As a result, the ability of data retention in the memory cell is decreased as erasing and programming are continuously repeated, resulting in a decrease in the reliability of an EEPROM. In order to solve such a problem, an erasing and programming technique employing an improved device, in which NAND cell units are formed on a P type well region formed on an N type semiconductor substrate, has been disclosed on pages 129 to 130 of xe2x80x9csymposium on VLSI Technologyxe2x80x9d published in 1990 under the title of xe2x80x9cA NAND STRUCTURED CELL WITH A NEW PROGRAMMING TECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY FLASH EEPROMxe2x80x9d. In the disclosures, the erasing operations of the memory cells, all the memory transistors within the NAND cell unit, are performed by applying 0 Volts to all the control gates and 20 Volts to the P type well region and the N type substrate. Electrons are evenly discharged from floating gates of all of the memory transistors to the P type wells. As a result, the threshold voltage of all of the memory transistors is converted to a negative voltage of xe2x88x924V, and the transistors become in a state of depletion mode from which a binary logic xe2x80x9c0xe2x80x9d is assumed as being stored therein. In order to program the selected memory transistors within the NAND cell unit, a high voltage of 20 V is applied to a gate of the first select transistor and a control gate of the selected memory transistor, 0 V to a gate of the second select transistor, and a middle voltage of 7 V to a control gate of each of the non-selected memory transistors, respectively. If the selected memory transistor is programmed by a binary logic xe2x80x9c1xe2x80x9d, 0 V is applied to bit lines coupled to the NAND cell unit, thereby the floating gate of the selected memory transistor is implanted with electrons and the selected memory transistor is converted to a state of enhancement mode. In contrast, if the selected memory transistor is programmed by a binary logic xe2x80x9c0xe2x80x9d, a middle voltage of 7V to prevent programming is applied to the corresponding bit lines, thereby the programming operation of the selected memory transistor is prevented. Since such a programming operation allows electrons to be evenly implanted into the floating gate through the gate oxide layer from the P type well, partial stress is not created in the thin gate oxide layer, preventing current leakage in the gate oxide layer.
When system designers wish to perform an erasing operation to reprogram a part or block of programmed or written memory cells, a problem occurs. In this case, a generally used method is to simultaneously erase (eg. flash erasing) all of the memory transistors within memory cell array and thereafter reprogram all the contents already programmed and new contents to be programmed.
Therefore, since even the part or block of memory cells that can still be used with the new program are simultaneously erased, it takes several, iterations, as well as being inconvenient to reprogram the new program and the existing program. Such an inconvenience will be severely created as capacity in a memory needs to become more and more increased. Erasing all of the memory transistors only within the selected memory block removes the majority of those problems. However, in the case of the EEPROM employing the foregoing improved erasing and programming technique, a high voltage more than 18 V or equal to the erasing voltage needs to be applied to a control gate of each of the memory transistors in the non-selected block to prevent the memory transistors from being erased.
As described above, the EEPROM design technique has continuously been improved for a relatively long time, and the NAND type Flash EEPROM accordingly created to have a flash erasing function can be advantageously applied as a large scaled sub-memory device because of the high degree of integration as compared with a common EEPROM. According to the type of the unit memory cell array of the flash EEPROM, the flash EEPROM is divided into a NAND type, NOR type, and NAND type. The NAND type has a higher integration degree than the Nor or AND type, as described above.
The NAND flash EEPROM memory cell is fabricated in such a manner that n-type regions to function as source and drain regions are formed on a P type substrate in a predetermined space from each other, thereafter, floating gate and control gate that are separated by an insulating layer are in order formed on an upper portion of a channel region placed between the source and drain regions. The conductive floating gate (FG) that is surrounded by the insulating layer is accumulated therein with charges that function as program data in response to a program voltage applied to the control gate (CG).
The erasing, writing and reading operations of the NAND type flash EEPROM are now explained below.
The erase and write operations are performed by utilizing F-N tunneling current. For instance, during an erasing operation, a high voltage is applied to a substrate and a low voltage is applied to a control gate (CG). In this case, a voltage is determined in response to the ratio of the capacitance between the CG and FG and the capacitance between the FG and the substrate, and the voltage is applied to the FG.
When the difference in potential between the floating gate voltage (Vfg) applied to the FG and the substrate voltage (Vsub) applied to the substrate is larger than the difference in potential that causes F-N tunneling, electrons in the FG begin to flow toward the substrate. As a result, the threshold voltage (Vt) of the memory cell transistor consisting of CG, FG, source and drain changes. Although 0V is applied to the CG and the source in a state that the Vt is sufficiently lowered, if current flows when a properly high voltage is applied to the drain, such a state is called xe2x80x9cERASEDxe2x80x9d and indicated logically as xe2x80x9c1xe2x80x9d. On the other hand to write data to a cell, 0 V is applied to a source and a drain and a very high voltage is applied to the CG. At this time, the channel region is formed therein with an inversion layer and the source and drain maintain an electric potential of 0V.
When the difference in electric potential that is applied between Vfg and channel voltage V channel (0V) that is determined by the capacitance ratio between the CG and FG and between the FG and channel region becomes so large as to create a F-N tunneling, electrons flow from the channel region to the FG. In this case, the Vt increases, and if electric current does not flow when a predetermined level of voltage is applied to the CG, 0V is applied to the source, and a proper level of voltage is applied to the drain, it is called xe2x80x9cPROGRAMMEDxe2x80x9d and indicated as logic xe2x80x9c0xe2x80x9d.
Even in the NAND flash memory as described above, the basic unit of a memory cell array, like the structure as previously described, includes a first select transistor, a second select transistor, and a cell string formed of a plurality of memory cell transistors in which drain-source channels are in series connected to each other and its FGs are formed between the first and second transistors. Wherein, it should be noted that the cell string may be also called a NAND cell unit in this field. The common NAND flash memory includes a memory cell array having a plurality of the cell strings, bit lines for inputting data to the cell strings and receiving data from the cell string, word lines crossed with the bit lines for controlling gates of the memory cell transistors and the select transistors in the cell string, an X decoder for selecting the word lines, page buffers connected to the bit lines to sense and store input/output data of the memory cell transistors, and a Y decoder circuit for controlling data input/output to the page buffers.
The page unit in the memory cell array structure indicates the memory cell transistors that are commonly connected to one word line at its control gates. The plurality of pages including a plurality of memory cell transistors is called cell block. One cell block unit generally includes one or a plurality of cell strings per bit line. One NAND flash memory as described above has a page program mode for a high-speed programming operation. The page program operation includes a data loading operation and a programming operation. The data loading operation is an operation for latching and storing data of byte size from input/output terminals in data registers. The data register is provided to correspond to each of the bit lines. The programming operation is an operation by which data stored in the data registers are simultaneously registered in memory transistors on a word line selected through bit lines. The page programming technique in an EEPROM having NAND cell units is disclosed in pages 417 to 423 of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.25, NO.2 issued April 1990.
As described above, the NAND flash memory generally performs a read operation and a program operation by a page unit and an erase operation by a block unit. Practically, the phenomenon that electrons flow between the FG and the channel of the memory cell transistor occurs in erase and program operations only. In a read operation, an operation of reading data stored in memory cell transistors without damaging the data occurs after the above-operations are ended.
In the read operation, a non-selected CG of NAND flash memory is supplied with a higher voltage than that supplied to a CG of selected memory. As a result, an electric current flows or does not flow in the corresponding bit lines in response to a programmed state of the selected memory cell transistor. In a predetermined voltage condition, if the threshold voltage of the programmed memory cell is higher than a reference voltage, the memory cell is identified as an off-cell and thereby the corresponding bit line is charged to a high level of voltage. In contrast, if the threshold voltage of the programmed memory cell is lower than a reference voltage, the memory cell is read as an on-cell, and thereby the corresponding bit line is discharged to a low level of voltage. Such a bit line state is finally read as xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d by a sense amplifier that is called a page buffer.
In this case, since there are many cell strings that are coupled to one bit line, the load amount in the bit line becomes large and the amount of current flowing through the on-cell during sensing the on-cell is small. Accordingly, as the voltage developing time grows relatively larger, the sensing time becomes longer. As a result, the reading time that it takes for the page buffer to read the stored date also increases resulting in a long read operation. In order to settle such an undesirable state, the NAND flash memory performs a page unit operation of page unit during a read operation. In the operation of a page unit, all data of the cells in one page are read at one time and the results are in order output, which is called a serial access. As a result, when the amount of data is large, data reading time per one bit is likewise reduced, thereby the relatively long sensing time can be compensated.
However, since the page unit operation randomly selects addresses to be read, its efficiency is remarkably reduced when accessing data or reading a small amount of data. That is, the access time that takes in reading data of one bit is nearly the same as that of reading data of one page.
Due to the characteristics of the NAND flash memory read operation, there is a problem in that the NAND flash memory is limited in its use in a memory application field that requires a random access of high-speed. For example, the NAND flash memory is limited in its use in the case that a small amount of data such as ROM table information or indexing information concerning data stored in a main memory cell array should be read with a higher speed than the read time of the flash memory cell array. Accordingly, advanced techniques are required to read data at a higher speed than in a random access of high-speed or an access to minor data.
Embodiments of the present invention provide a nonvolatile semiconductor memory by which data can be read in a higher speed than in a random access of high-speed or an access to minor data.
Embodiments of the present invention provide a nonvolatile semiconductor memory cell array structure having a reduced read operation time that is useable in fields requiring high-speed random access, in a NAND type clash memory array
According to embodiments of the invention, a high-speed random access is selectively performed in a same memory. The structure can be used in the memory application field that requires a high speed in randomly reading minor data and ROM tables for a high-speed read.